Chip Design Academy

  📘 Basics of Physical Design Physical Design is the process of converting the synthesized netlist (from RTL) into a layout that can be manufactured on silicon. This stage starts after logic synthesis and ends with GDSII generation. 🔹 RTL to GDSII Flow Overview Logic Synthesis → Netlist generation Floorplanning → Die/core planning, power grid setup Placement → Standard cell placement and legalization Clock Tree Synthesis (CTS) → Distribution of clock with minimal skew Routing → Global + detailed routing of signals Timing Closure → Fix setup/hold, IR drop, noise Signoff → DRC, LVS, ERC checks before tapeout 🔹 Key Constraints Constraint Description Timing Meet setup and hold requirements across all paths. Area Optimize utilization to reduce die size. Power Manage leakage, dynamic power, and IR drop. 🔹 Inte...

  Chip Design Academy Your guide to VLSI Physical Design & Verification Welcome Explore step-by-step concepts in VLSI Physical Design from Floorplanning to Tapeout. Each section below will guide you with explanations, diagrams, and interactive learning. 📚 Physical Design Topics Click on a topic to expand and learn more: 1. Basics of Physical Design ASIC Flow Overview (RTL → GDSII) Constraints: Timing, Area, Power Design Environment Setup 2. Floorplanning Core vs. Die, Utilization Power Planning (straps, rings) Macro Placement 3. Placement Standard Cell Placement Legalization Congestion Analysis 4. Clock Tree Synthesis (CTS) Skew & Latency H-Tree, Mesh, Spine Useful Skew ...

 Hi, I’m Praveen i, a VLSI Physical Design engineer passionate about sharing knowledge on ASIC/SoC flows.  This blog covers floorplanning, placement, CTS, routing, and sign-off to help students and engineers  understand chip design concepts step by step.