Basics of Physical Design

 

📘 Basics of Physical Design

Physical Design is the process of converting the synthesized netlist (from RTL) into a layout that can be manufactured on silicon. This stage starts after logic synthesis and ends with GDSII generation.

🔹 RTL to GDSII Flow Overview

• Logic Synthesis → Netlist generation
• Floorplanning → Die/core planning, power grid setup
• Placement → Standard cell placement and legalization
• Clock Tree Synthesis (CTS) → Distribution of clock with minimal skew
• Routing → Global + detailed routing of signals
• Timing Closure → Fix setup/hold, IR drop, noise
• Signoff → DRC, LVS, ERC checks before tapeout

🔹 Key Constraints

Constraint	Description
Timing	Meet setup and hold requirements across all paths.
Area	Optimize utilization to reduce die size.
Power	Manage leakage, dynamic power, and IR drop.

🔹 Interactive Quiz

Q: Which step comes immediate