Chip Design Academy

Your guide to VLSI Physical Design & Verification

Welcome

Explore step-by-step concepts in VLSI Physical Design from Floorplanning to Tapeout. Each section below will guide you with explanations, diagrams, and interactive learning.

📚 Physical Design Topics

Click on a topic to expand and learn more:

1. Basics of Physical Design

• ASIC Flow Overview (RTL → GDSII)
• Constraints: Timing, Area, Power
• Design Environment Setup

2. Floorplanning

• Core vs. Die, Utilization
• Power Planning (straps, rings)
• Macro Placement

3. Placement

• Standard Cell Placement
• Legalization
• Congestion Analysis

4. Clock Tree Synthesis (CTS)

• Skew & Latency
• H-Tree, Mesh, Spine
• Useful Skew

5. Routing

• Global vs Detailed Routing
• Routing Rules & DRC
• Signal Integrity (Crosstalk, Shielding)

6. Timing Closure

• Setup & Hold Analysis
• STA Basics
• ECO for Timing Fixes

7. Power Analysis

• IR Drop, EM
• Clock Gating
• Power Gating

8. Physical Verification & Signoff

• DRC, LVS, ERC
• Antenna Checks
• Signoff Tools (Calibre, ICV)

© 2025 Chip Design Academy | Created by Praveen Kumar Naddi

Chip Design Academy

Learn VLSI Physical Design & Verification

Home Basics Floorplanning Placement CTS Routing Timing

Basics of Physical Design

Introduction to VLSI flow, design stages, netlists, and PnR overview.

Floorplanning

Understand die size estimation, macro placement, power planning, and I/O design.

Placement

Learn about standard cell placement, congestion management, and legalization.

Clock Tree Synthesis

Balancing skew, insertion delay, and clock distribution techniques.

Routing

Detail routing, DRC fixing, antenna rules, and signal integrity handling.

Timing Closure

Static Timing Analysis (STA), ECOs, and achieving sign-off timing closure.

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